1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a technique of utilizing a defective chip as a partially good chip.
2. Description of the Related Art
As a method for improving yields and thereby providing a semiconductor memory product at low cost, a technique for recovering a defective chip into a partially good chip (see, e.g., Japanese Patent Laid-Open No. Hei 3-168998 and Japanese Patent Laid-Open No. Hei 8-297996) is known. For example, if a chip with a storage capacity of 512 Mbits is detected to be partially defective, it is possible to recover the chip into a chip with a storage capacity of, e.g., 256 Mbits by barring access to a defective part of a memory cell array of the chip.
Known methods for recovering a defective chip into a partially good chip include a method of fixing a value of a part of an internal address. FIGS. 1A and 1B are conceptual diagrams showing examples of the method for recovering the defective chip into the partially good chip by fixing the value of the part of the internal address. In examples in FIGS. 1A and 1B, a semiconductor memory device in which each of four banks are addressed using two bank address bits BA0 and BA1, and a memory cell of each bank is addressed using 13 address bits A0 to A13 serves as an object to be recovered.
For example, if defects are present only in areas of a memory cell array whose uppermost address bit A13 is “0”, as shown in FIG. 1A, each uppermost address bit A13 is fixed at “1”. This only allows access to the areas whose uppermost address bit A13 is “1”, and the semiconductor memory device is recovered into a chip with a half storage capacity. In FIG. 1A, inaccessible areas are hatched. The chip obtained after such recovering is called an “address-based partially good product”.
If defects are present only in banks (banks 2 and 3) whose upper bank address bit BA1 is “1”, as shown in FIG. 1B, each upper bank address bit BA1 is fixed at “0”. This only allows access to banks 0 and 1, and the semiconductor memory device is recovered into a chip with a half storage capacity. In FIG. 1B, inaccessible banks are hatched. The chip obtained after such recovering is called a “bank-based partially good product”.
FIG. 2 is a flow chart showing an example of a set of subsequent processes for recovering a defective chip into a partially good chip. First, a first wafer test process is performed (step S01). In the first wafer test process, a wafer for which a preceding process (diffusion process) has been performed is subjected to a probe test. The defective bit is detected by this test.
A trimming process is then performed (step S02). In the trimming process, metal fuses integrated on each chip are trimmed. The metal fuse trimming has two purposes. The first is to perform redundancy relief, which replaces a defective bit with a relief bit. The correspondence between an external address and an internal address is changed by trimming metal fuses prepared for the redundancy relief. With this relief, the defective bit is replaced with the relief bit. The second is to recover a defective chip into a partially good chip. If a defective bit is present outside a range that can be relieved by the redundancy relief, the value of a part of the internal address is fixed by trimming metal fuses prepared separately from ones for the redundancy relief. With this relief, the defective chip is recovered into the partially good chip.
After the trimming process, a second wafer test process is performed (step S03). In the second wafer test process, it is checked whether the defective bit has been correctly relieved by the redundancy relief. After the second wafer test process, each chip is assembled into a package in an assembly process (step S04). The assembled package is tested in a screening test process (step S05). Packages which have been determined to be the good product in the screening test process are shipped.
If it is determined in the second wafer test process that the defective bit to be relieved has not been relieved by the redundancy relief, the defective chip having the defective bit is recovered into the partially good chip when possible. More specifically, the part of the internal address is fixed by bonding the defective chip to a bonding pad which activates a signal for fixing the value of the part of the internal address in the assembly process. With this operation, access to an area including the defective bit is barred, and the defective chip is recovered into the partially good chip.
One problem with the above-described procedure is that recovering of the defective chip into the partially good chip cannot be performed after the assembly process. More specifically, even if the defective bit is detected in the screening test process, the defective chip with the defective bit cannot be recovered into the partially good chip. In the screening test after the assembly process, there is a possibility that the defective bit which has not been detected in the second wafer test process is detected. One reason for the possibility is that both the tests are different in test conditions (e.g., operating speed and test temperature). Another reason is that some bits may become defective due to change in characteristics caused by thermal stress or mechanical stress in the assembly process. A chip with the defective bit detected in the screening test should conventionally be rejected and discarded. This is undesirable from the viewpoint of improving yields and reducing costs. There is a demand for a technique for recovering the defective chip into the partially good chip even after the assembly process.